Field of the Invention
Embodiments of the present disclosure relate to a bit line equalizer for precharging and/or equalizing pairs of bit lines, and more particularly to a layout structure of a bit line equalizer configured to minimize the height of the bit line equalizer.
Description of Related Art
Generally, semiconductor memory devices such as Dynamic Random Access Memories (DRAMs) may include a plurality of memory cell arrays composed of a plurality of memory cells configured to store data therein. They may also include a plurality of sense-amplifiers disposed between the plurality of memory cell arrays to sense and amplify data stored in the memory cells. Respective sense-amplifiers may be coupled to bit lines and inverted bit lines (also called bit line bars), and may sense and amplify data signals of the bit lines and the inverted bit lines. The above-mentioned operation for sensing and amplifying the data signals using sense-amplifiers will be described in detail hereinafter.
Each bit line and each inverted bit line may be precharged with a predetermined bit line voltage before each word line is enabled. If the word line is enabled, each cell transistor of each memory cell may be turned on, and a data signal corresponding to data stored in the cell may be applied to the bit line by sharing charges between the cell capacitor of the memory cell and the bit line.
The sense-amplifier may detect a difference between a bit-line voltage of the precharged inverted bit line and a data signal of the bit line, amplify the detected difference, and then read data stored in the memory cell.
Since the difference between the bit line voltage and the data signal is very small, it is necessary for the bit line and the inverted bit line to be precharged with the same bit line voltage before the word line is enabled, such that the precharged bit line voltages need to be maintained. For this purpose, the sense-amplifier may include a bit line equalizer configured to maintain the bit line and the inverted bit line at the same bit line voltage.
FIGS. 1 and 2 are circuit diagrams illustrating conventional bit line equalizers, and FIG. 3 is a layout structure illustrating the bit line equalizers shown in FIG. 2.
Referring to FIG. 1, the bit line equalizer (EQ) may include an equalize transistor N1 and precharge transistors (N2, N3) coupled between the bit line (BL) and the inverted bit line (BLb).
The precharge transistors (N2, N3) may precharge the bit line (BL) and the inverted bit line (BLb) with a bit line precharge voltage (VBLP).
The equalize transistor N1 may equalize the bit line (BL) and the inverted bit line (BLb) in response to an equalize signal (EQ_s), so that the bit line (BL) and the inverted bit line (BLb) can be maintained at the same bit line precharge voltage (VBLP).
With the increasing integration degree of the semiconductor device, a “⊥”-shaped equalizer shown in FIG. 1 has been gradually modified to a “——”shaped equalizer shown in FIG. 2. The equalizer shown in FIG. 2 includes the equalize transistor N1 and the precharge transistors (N2, N3) coupled in series to the equalize transistor N1, and has a layout structure shown in FIG. 3.
However, if transistors are formed as shown in FIG. 2, the height of each transistor is unavoidably increased.